The present invention relates to a nonvolatile memory device, in particular of flash type.
As is known, the increasing demand for high density memories has led to the design of nonvolatile memory structures having an increasingly compact architecture.
For this reason, nonvolatile memories that store information in binary format in floating gate memory cells are increasingly widespread. FIG. 1 shows, for example, the structure of a flash memory cell 1 which has a floating gate region 2 and a control gate region 3 overlying a P-type substrate 4, where an N-type source region 5 and an N-type drain region 6 are integrated. For storing information, electric charges are injected from the substrate 4 into the floating gate region 2 (programming operations), so varying the threshold of the memory cell, i.e., the voltage to be applied between the source region 5 and the control gate region 3 to obtain turning-on of the memory cell 1 and conduction of electric current between the source region 5 and the drain region 6. The read operation detects the conductive characteristic of the cells, converting it into information. The operation of removing electric charge stored in the floating gate region 2, referred to as xe2x80x9cerasingxe2x80x9d, is carried out differently according to the memory type. In particular, in high compactness flash memories, the source regions of the cells of one part of the memory are connected together and are erased simultaneously by biasing the source region 5 and possibly also the substrate 4 with high positive voltages (typically, of between +5 and +8 V). The portions of memory in which the cells have source regions connected together are called xe2x80x9csectorsxe2x80x9d.
FIG. 2 shows the structure of a memory cell 1 formed in a triple well. As may be noted, the P-type substrate 4 houses an N-type external well 10, which in turn houses a P-type isolated well 11 (constituting the body region), where the source region 5 and drain region 6 are housed. In FIG. 3, the memory cells 1 belonging to a same sector are all housed in the same isolated well 11, and the cells of two sectors 15.0 and 15.1 are housed in two separate isolated wells, 11.0 and 11.1, and two separate external wells, 10.0 and 10.1.
The division of the memory array into a number of sectors and the size of these sectors, which yields the resolution of the erasing operation, depend upon the specific needs of the applications. It is evident that the higher the memory density, the greater the likelihood of having to divide the array into a large number of sectors, which are each to be erased separately.
In flash memories of the multilevel type (in which each memory cell stores more than one bit), the information density per unit area grows further, just as the need to have sufficiently subdivided sectors.
The division into sectors is conditioned not only by the applications, but also by the process parameters (defectiveness and management of redundancy, as well as band-to-band tunneling current if the source region 5 and the isolated well 11 are at different erasing potentials).
For example, each sector may comprise between 1 and 2 Mb; in some applications, divisions into non-uniform sectors are necessary, and sectors of very small size are required (for example, 16 kb or 32 kb) to contain the bootstrap code of the microprocessor and the parameters for the bootstrap separately.
Inside a flash memory, regardless of how the sectors are organized (by rows or by columns), it is essential to bias the source regions, and possibly the isolated wells 11 of the cells, as well as the respective external wells 10, in an independent way. In addition, also during programming it may be advantageous to bias the isolated well 11 of the selected sector; in fact, by biasing the isolated well 11 at a negative potential (ranging between xe2x88x921 and xe2x88x922 V), it is possible to obtain better performance in terms of programming speed. For instance, a triple well flash cell, as shown in FIG. 2, can be biased in the way illustrated in the following Table I, using the body terminal B for the isolated well 11 and the N-well terminal W for the external well 10.
It is therefore of fundamental importance to control each sector independently of the others to prevent undesired electrical stresses on the source terminal (xe2x80x9csource stressxe2x80x9d or xe2x80x9csoft erasingxe2x80x9d).
In case of large size memory arrays, this involves a considerable complexity for controlling the sectors. In fact, for each sector it is necessary to provide MOS switches to connect it to the high voltage during erasing, to connect its terminals to ground during reading, and to bias the isolated well 11 at a negative voltage during programming. For example, in case of a 64 Mb flash memory divided into 64 equal sectors of 1 Mb each, if each sector has an own enabling signal and own signals for managing the operation being carried out (programming, reading, erasing, erasing and programming verify), the following signals and switches are necessary (see in particular FIG. 4):
64 sector enabling signals S-EN, one for each sector, to be decoded starting from the address vector defining them uniquely and to be supplied to a respective sector switch. Since the memory cells are arranged in a matrix (i.e., in rows and columns), the sector enabling signals must traverse areas adjacent to the rows and columns of the memory banks;
at least two control signals CS, one for erasing, which controls the positive erasing biasing, and one for programming, which controls the negative biasing of the isolated well 11. Both inactive signals could represent the read condition (source terminal S and body terminal B to ground);
sector switches (formed by enabling transistors or pass transistors of the PMOS and NMOS types), both positive and negative, for biasing the source terminal S, the body terminal B and the N-type well W of each sector;
a control logic for each sector, which decodes the signals to be applied to the sector switches according to the operating mode;
high voltage analog switches, which enable the sector switches (both PMOS and NMOS) to be turned off in presence of voltages having a higher value than the supply voltage. In fact, as is known, positive voltages greater than the supply voltage are advantageously transferred by PMOS transistors, and negative voltages are advantageously transferred by NMOS transistors.
In FIG. 4, the sector switches PT, the control logic LOGIC, and the analog high voltage switches HVS of each sector are gathered together in a single block 16 for simplicity.
FIGS. 5 and 6 show, respectively, possible implementations of high voltage analog switches of positive and negative type wherein IN represents the input signal, O and ON represent the output signal and its inverted signal, respectively; Vdd is the supply voltage; Vpp is a positive voltage higher than the supply voltage, for example the programming voltage; and VNEG is a negative voltage, for example the body voltage during programming.
It is evident that this organization requires a high use of the area necessary, above all, for arranging the interconnections of the enabling signals and the high voltage switches HVS.
Even if the biasing terminals of the sectors were brought to another point of the memory device and the decoding control logic circuits were grouped together there, a considerable space would be required to implement the signal buses. In addition, these buses could not be managed with metal lines of minimal width, in that the current flowing during charging and discharging of the terminals is a few mA.
In the example cited above of 64 sectors with three terminals, i.e., one body terminal, one N-well terminal, and one source terminal, for each sector three P-channel pass transistors (and corresponding positive switches) should be implemented to bring onto each terminal the high positive voltage required for erasing, and an N-channel pass transistor (and corresponding negative switch) for the negative body voltage. Consequently, 256 switching circuits would be required, which would occupy a large amount of space given that each one of them requires from 6 to 10 MOS transistors.
An embodiment of the invention provides an architecture enabling biasing of the sectors with a smaller area bulk.
An embodiment of the present invention is directed to a memory device that includes a plurality of memory sectors, a plurality of switching stages, a plurality of groups of biasing lines, and a plurality of decoding stages, one for each of the first alignment lines. Each memory sector includes a plurality of memory cells and the memory sectors are mutually aligned along a plurality of first alignment lines parallel to one another and along a plurality of second alignment lines parallel to one another and perpendicular to the first alignment lines. Each switching stage is connected to a respective one of the memory sectors. The groups of biasing lines extend parallel to the first alignment lines and each group of biasing lines is connected by a respective set of the switching stages to the memory sectors aligned along a respective one of the first alignment lines. The decoding stages are connected between reference potential lines and a respective one of the groups of biasing lines. Such an arrangement implements a hierarchical decoding of the memory sectors.
In practice, the memory device enables selecting the sectors in a unique way, using high voltage pass lines and enabling signals appropriately shared by rows and columns of sectors, for example, by getting the rows of sectors to share the high voltage lines, and the columns of sectors to share the enabling signals.